Last month we told you that Huawei has found a way around the U.S. sanctions that prevent it and Chinese foundries from obtaining the cutting-edge lithography machines needed to produce chips using advanced process nodes. Only one company, ASML, makes the extreme ultraviolet (EUV) lithography machines that can print intricate circuitry patterns onto the silicon wafers that are the foundation of the chips.
Advanced lithography machines cannot be shipped to China
ASML can still ship Deep Ultraviolet lithography machines to China, but only those models that are dry and don’t use water between the lens and the wafer that refracts light, allowing finer lines to be printed. The inability of Chinese companies and foundries to get their hands on any lithography machines more capable than Dry Deep Ultraviolet Lithography machines severely limits Huawei and other tech firms in China.
Being unable to obtain lithography machines with short light wavelengths means that companies like Huawei can, at best, get their hands on 7nm chips, perhaps 5nm using a technique called multiple patterning. The latter creates finer features on the silicon wafer by splitting a complex pattern into two or more patterns that are less dense.
Huawei announces a major breakthrough in chip manufacturing
Recently, Huawei announced a major breakthrough that it says will allow it to produce chips with a transistor density equivalent to a 1.4nm chip by 2031. To compare, TSMC is expected to mass-produce 1.4nm chips starting in 2028. The transistor density is expressed as the millions of transistors/square millimeter and the larger the number, the greater the performance of the chip.
Chip scientist Andrew B. Kahng says Huawei’s plan to make competitive chips without an EUV machine is viable. | Image by UC San Diego
That’s because the shorter the distance between transistors, the faster electrical signals can travel, increasing clock and processing speeds. Smaller transistors also require less power to switch on and off conserving energy. The ability to fit more components on a wafer allows foundries to produce more chips per batch, which, over time, reduces the cost of the chip.
Last month Huawei introduced a new architecture called LogicFolding
Huawei introduced a new process in May at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, based on the Tau Scaling Law, which reduces the time it takes signals and data to move through chips and computing systems. It does this using an architecture known as LogicFolding, a process that stacks logic circuits vertically into multiple layers.
This technique shortens wiring, reducing the distance signals must travel. This also helps to reduce issues that can drop processing speeds. And most importantly, stacking circuits on top of each other will allow Huawei to obtain chips with the transistor density equivalent of a 1.4nm chipset.
LogicFolding could replace Moore’s Law
To be clear, let’s examine what Huawei plans. Geometric scaling is the current method used to reduce the size of the transistors to improve transistor density and to make a chip more powerful and energy efficient. Instead, Huawei is reducing the time it takes for signals to move through the elements of a chip.
This is bombshell news because the concern has been that Moore’s Law, the observation made by Fairchild and Intel co-founder Gordon Moore, is coming to an end. Moore noted that the number of transistors in a chip would double every other year. But there is a physical limit to how much more you can shrink the size of a transistor.
Huawei’s new approach might help the beleaguered company power its new devices with competitive chips. LogicFolding could also be the technique that allows more powerful chips to be designed and manufactured after it becomes impossible to shrink transistors and make them smaller.
